1. The Field of the Invention
The present invention relates to fabrication of semiconductor structures. More particularly, the present invention relates to the formation of conductive and insulative layers in semiconductor structures. In particular, the present invention relates to the formation of metal silicide and nitride layers upon active areas on shallow junctions, upon gate structures, upon local interconnects, upon contacts, upon landing pads, and the like.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above. The term semiconductor substrate is contemplated to include such structures as silicon-on-insulator and silicon-on-sapphire.
In the microelectronics industry, the process of miniaturization entails the shrinking of individual semiconductor devices and crowding more semiconductor devices into a given unit area. With miniaturization, problems and complications incurred during processing lower the overall processing yield of the semiconductor devices. Each additional step required in the multiple processing steps increases the likelihood of individual mistakes upon a given wafer that, singularly or collectively, will cause a given microelectronic circuit to fail during testing or to fail unacceptably early in the field.
An example of multiple processing steps in the prior state of the art includes the formation of contacts to active areas in semiconductor devices. FIG. 1 illustrates a semiconductor structure 10 comprising a semiconductive substrate 12 that is exposed through an oxide 14. Within semiconductive substrate 12, an active area 16 is formed such as by N-doping within a P-well or vice-versa. The depth of active area 16 is illustrated as ajunction 18. During the formation of interconnects, it has been a conventional practice to place a titanium layer 20 over semiconductor structure 10, as seen in FIG. 2, to assist with electrical connection and to prevent aluminum spiking into semiconductive substrate 12 through active area 16.
Titanium layer 20 of FIG. 2 is heat treated in the presence of nitrogen to form a TiN reaction layer 24 seen in FIG. 3. FIG. 3 depicts the prior art structure of FIG. 2 after several subsequent processing steps that follow deposition of titanium layer 20. Alternatively, formation of a TiN layer may be carried out by nitrogen implantation into Ti layer 20. Optionally, further formation of TiN reaction layer 24 may be carried out by thermal processing of the implanted nitrogen.
During the heat treatment, a TiSi.sub.2 reaction layer 22, seen in FIG. 3, is formed by reaction of titanium layer 20 with the silicon within active area 16. Immediately above TiSi.sub.2 reaction layer 22, there remains a portion of unreacted titanium 26 as the residue of titanium layer 20. Thermal processing also causes upper portions of titanium layer 20, as depicted in FIG. 2, to form TiN reaction layer 24. A metallization layer 28 is deposited upon TiN reaction layer 24 within a recess in oxide 14 where the recess terminates at active area 16.
In the formation of semiconductor structures such as a static random access memory (SRAM) structure, it is necessary to isolate individual components and to interconnect others, for example by etching through metallization layer 28, TiN reaction layer 24, and titanium layer 20. Because of the different chemical qualities of each of the aforementioned layers, the etch chemistry may require several individual etch recipes and processing steps.
Etching is illustrated as having been carried out in FIG. 3 upon semiconductor structure 10 whereby a patterning mask 30 has been formed and patterned upon metallization layer 28, and whereby the formation of a breach 42 has been accomplished by several etching steps.
FIG. 4 is an elevational cross-section detail of a portion of semiconductor structure 10 depicted in FIG. 3 taken alone the 4--4 section line, wherein it can be seen that patterning of metallization layer 28 results in an undercut 44 beneath TiN reaction layer 24 into unreacted Ti 26. Undercut 44 is caused by the requirement of multiple etch recipes in order to form breach 42, and by the nature of unreacted Ti 26 which etches significantly faster than TiN reaction layer 24. It can be seen in FIG. 4 that undercut 44 is formed within semiconductor structure 10 above oxide 14. Undercut 44 of TiN reaction layer 24 into unreacted Ti 26 can cause the collapse of structures that are superficial thereto, unwanted shorting, lift off, and other problems.
In addition to the possibility of the formation of undercut 44, the chemical composition of TiN reaction layer 24 contains a titanium-nitrogen gradient. The gradient of TiN reaction layer 24 begins with a lower surface 46 that is rich in titanium ("Ti-rich") and ends with an upper surface 48 that has less titanium therein ("Ti-lean"). Thus, the etch recipe for TiN reaction layer 24 must be selected to be broad enough to etch through lower surface 46 after etching through upper surface 48. In some cases, substantially complete etching of TiN reaction layer 24 would be required to be carried out by at least two etches to accommodate Ti-rich lower surface 46 and Ti-lean upper surface 48.
An additional problem that occurs by this prior art method is the possibility of formation of excessive amounts of TiSi.sub.2 reaction layer 22 within the region of active area 16. A thermal process will be carried out to cause some or all of the titanium within titanium layer 20 upon active area 16 to form TiSi.sub.2. If titanium layer 20 is deposited in excess, TiSi.sub.2 reaction layer 22 could expand entirely through junction 18, thereby destroying it. Where titanium layer 20 is deposited in excess, a process engineer may choose to thermally treat semiconductor structure 10 for a limited time period. The limited time period will allow for a desired amount of titanium layer 20 and active area 16 to form TiSi.sub.2. The process window for such an achievement may be too narrow to avoid undesirable results. The process engineer must thus balance a proper amount of deposition of titanium layer 20 against the thermal budget for the fabrication processing. Also, the process engineer must balance formation of TiSi.sub.2 reaction layer 22 with the thermal budget and other activities such as annealing of dopants within active area 16. Finally, the process engineer that uses the prior art technique must balance thermal processing with potentially multiple and varied etch recipes in order to form breach 42 without the formation of undercut 44.
What is needed in the art is a method that overcomes the problems in the prior art, including a method of forming a TiSi.sub.2 reaction layer that overcomes the problem of excessive TiSi.sub.2 formation from a titanium layer that could potentially consume an active area so as to cause junction defects or defects in other structures.
What is also needed in the art is a method of forming a TiSi.sub.2 reaction layer that avoids the possibility of a multiple, complicated, and broad etch that is required to remove a TiN reaction layer that comprises a Ti concentration gradient, and to remove an unreacted Ti layer without the destructive effects of undercutting.
What is also needed in the art is a method of forming a TiSi.sub.2 conversion layer that avoids the problem of undercutting a TiN reaction layer into unreacted titanium.